Power balanced pipelines

John Sartori, Ben Ahrens, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been a primary design objective, as it maximizes instruction throughput. Unfortunately, this causes significant energy inefficiency in processors, as each microarchitectural pipeline stage gets the same amount of time to complete, irrespective of its size or complexity. For power-optimized processors, the inefficiency manifests itself as a significant imbalance in power consumption of different microarchitectural pipestages. In this paper, rather than balancing processor pipelines for delay, we propose the concept of power balanced pipelines - i.e., processor pipelines in which different delays are assigned to different microarchitectural pipestages to reduce the power disparity between the stages while guaranteeing the same processor frequency/performance. A specific implementation of the concept uses cycle time stealing [19] to deliberately redistribute cycle time from low-power pipeline stages to power-hungry stages, relaxing their timing constraints and allowing them to operate at reduced voltages or use smaller, less leaky cells. We present several static and dynamic techniques for power balancing and demonstrate that balancing pipeline power rather than delay can result in 46% processor power reduction with no loss in processor throughput for a full FabScalar processor over a power-optimized baseline. Benefits are comparable over a Fabscalar baseline where static cycle time stealing is used to optimize achieved frequency. Power savings increase at lower operating frequencies. To the best of our knowledge, this is the first such work on microarchitecture- level power reduction that guarantees the same performance.

Original languageEnglish (US)
Title of host publicationProceedings - 18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012
Number of pages12
StatePublished - 2012
Event18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012 - New Orleans, LA, United States
Duration: Feb 25 2012Feb 29 2012

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897


Other18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012
Country/TerritoryUnited States
CityNew Orleans, LA

ASJC Scopus subject areas

  • Hardware and Architecture


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