Postplacement voltage assignment under performance constraints

Huaizhi Wu, Martin D.F. Wong, Wilsin Gosti

Research output: Contribution to journalArticlepeer-review

Abstract

Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to control the complexity of the power-supply system and limit the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm was proposed for generating voltage islands that balance the power-versus-design-cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite of this algorithm is an initial voltage assignment at the standard-cell level that meets timing. In this article, we present a novel method to produce quality voltage assignment which not only meets timing but also forms good proximity of the critical cells to provide a smooth input to the aforementioned voltage island generation. Our algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our extensive experiments on real industrial designs show that our algorithm leads to 25% - 75% improvement in the voltage island generation in terms of the number of voltage islands generated, with computation time only linear to design size.

Original languageEnglish (US)
JournalACM Transactions on Design Automation of Electronic Systems
Volume13
Issue number3
DOIs
StatePublished - Jul 1 2008

Keywords

  • Low power
  • Timing
  • Voltage assignment
  • Voronoi diagram

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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