Abstract
Programming heterogeneous parallel systems can be extremely complex because a single system may include multiple different parallelism models, instruction sets, and memory hierarchies, and different systems use different combinations of these features. We propose a carefully designed parallel abstraction of heterogeneous hardware-a hierarchical dataflow graph with shared memory and vector instructions-that is able to capture the parallelism in a wide range of popular parallel hardware. We use this abstraction, which we call hVISC, to define a Virtual Instruction Set Architecture (ISA) that aims to address both functional portability and performance portability across heterogeneous systems. hVISC is more general than existing virtual instruction sets such as PTX, HSAIL and SPIR, e.g., it can capture both streaming parallelism and general dataflow parallelism.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 443-445 |
| Number of pages | 3 |
| Journal | Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT |
| DOIs | |
| State | Published - Jan 1 2016 |
| Event | 25th International Conference on Parallel Architectures and Compilation Techniques, PACT 2016 - Haifa, Israel Duration: Sep 11 2016 → Sep 15 2016 |
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Keywords
- CUDA
- GPU
- heterogeneous systems
- multicore
- opencl
- parallel compiler ir
- ptx
- virtual instruction set
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
Cite this
POSTER : HVISC: A Portable Abstraction for Heterogeneous Parallel Systems. / Srivastava, Prakalp; Kotsifakou, Maria; Sinclair, Matthew D.; Komuravelli, Rakesh; Adve, Vikram Sadanand; Adve, Sarita V.
In: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 01.01.2016, p. 443-445.Research output: Contribution to journal › Conference article
}
TY - JOUR
T1 - POSTER
T2 - HVISC: A Portable Abstraction for Heterogeneous Parallel Systems
AU - Srivastava, Prakalp
AU - Kotsifakou, Maria
AU - Sinclair, Matthew D.
AU - Komuravelli, Rakesh
AU - Adve, Vikram Sadanand
AU - Adve, Sarita V
PY - 2016/1/1
Y1 - 2016/1/1
N2 - Programming heterogeneous parallel systems can be extremely complex because a single system may include multiple different parallelism models, instruction sets, and memory hierarchies, and different systems use different combinations of these features. We propose a carefully designed parallel abstraction of heterogeneous hardware-a hierarchical dataflow graph with shared memory and vector instructions-that is able to capture the parallelism in a wide range of popular parallel hardware. We use this abstraction, which we call hVISC, to define a Virtual Instruction Set Architecture (ISA) that aims to address both functional portability and performance portability across heterogeneous systems. hVISC is more general than existing virtual instruction sets such as PTX, HSAIL and SPIR, e.g., it can capture both streaming parallelism and general dataflow parallelism.
AB - Programming heterogeneous parallel systems can be extremely complex because a single system may include multiple different parallelism models, instruction sets, and memory hierarchies, and different systems use different combinations of these features. We propose a carefully designed parallel abstraction of heterogeneous hardware-a hierarchical dataflow graph with shared memory and vector instructions-that is able to capture the parallelism in a wide range of popular parallel hardware. We use this abstraction, which we call hVISC, to define a Virtual Instruction Set Architecture (ISA) that aims to address both functional portability and performance portability across heterogeneous systems. hVISC is more general than existing virtual instruction sets such as PTX, HSAIL and SPIR, e.g., it can capture both streaming parallelism and general dataflow parallelism.
KW - CUDA
KW - GPU
KW - heterogeneous systems
KW - multicore
KW - opencl
KW - parallel compiler ir
KW - ptx
KW - virtual instruction set
UR - http://www.scopus.com/inward/record.url?scp=84989282504&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84989282504&partnerID=8YFLogxK
U2 - 10.1145/2967938.2976039
DO - 10.1145/2967938.2976039
M3 - Conference article
AN - SCOPUS:84989282504
SP - 443
EP - 445
JO - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
JF - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
SN - 1089-795X
ER -