Abstract
Programming heterogeneous parallel systems can be extremely complex because a single system may include multiple different parallelism models, instruction sets, and memory hierarchies, and different systems use different combinations of these features. We propose a carefully designed parallel abstraction of heterogeneous hardware-a hierarchical dataflow graph with shared memory and vector instructions-that is able to capture the parallelism in a wide range of popular parallel hardware. We use this abstraction, which we call hVISC, to define a Virtual Instruction Set Architecture (ISA) that aims to address both functional portability and performance portability across heterogeneous systems. hVISC is more general than existing virtual instruction sets such as PTX, HSAIL and SPIR, e.g., it can capture both streaming parallelism and general dataflow parallelism.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 443-445 |
| Number of pages | 3 |
| Journal | Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT |
| DOIs | |
| State | Published - 2016 |
| Event | 25th International Conference on Parallel Architectures and Compilation Techniques, PACT 2016 - Haifa, Israel Duration: Sep 11 2016 → Sep 15 2016 |
Keywords
- CUDA
- GPU
- heterogeneous systems
- multicore
- opencl
- parallel compiler ir
- ptx
- virtual instruction set
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture