Positional adaptation of processors: Application to energy reduction

Michael C. Huang, Jose Renau, Josep Torrellas

Research output: Contribution to journalConference article

Abstract

Although adaptive processors can exploit application variability to improve performance or save energy, effectively managing their adaptivity is challenging. To address this problem, we introduce a new approach to adaptivity: the Positional approach. In this approach, both the testing of configurations and the application of the chosen configurations are associated with particular code sections. This is in contrast to the currently-used Temporal approach to adaptation, where both the testing and application of configurations are tied to successive intervals in time. We propose to use subroutines as the granularity of code sections in positional adaptation. Moreover, we design three implementations of subroutine-based positional adaptation that target energy reduction in three different workload environments: embedded or specialized server, general purpose, and highly dynamic. All three implementations of positional adaptation are much more effective than temporal schemes. On average, they boost the energy savings of applications by 50% and 84% over temporal schemes in two experiments.

Original languageEnglish (US)
Pages (from-to)157-168
Number of pages12
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - Jul 17 2003
Event30th Annual International Symposium on Computer Architecture - San Diego, CA, United States
Duration: Jun 9 2003Jun 11 2003

ASJC Scopus subject areas

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Positional adaptation of processors: Application to energy reduction'. Together they form a unique fingerprint.

  • Cite this