Polynomial time optimal algorithm for stencil row planning in e-beam lithography

Daifeng Guo, Yuelin Du, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Electron beam lithography (EBL) is a very promising candidate for integrated circuit (IC) fabrication beyond the 10 nm technology node. To address its throughput issue, the Character Projection (CP) technique has been proposed, and its stencil planning can be optimized with aware of overlapping characters. However, the top level 2D stencil planning problem has been proved to be an NP-hard problem. As its most essential step, the 1D row ordering is believed hard as well, and no polynomial time optimal solution has been provided so far. In this paper, we propose a polynomial time optimal algorithm to solve the row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Proof and experimental results are also provided to verify the correctness and efficiency of our algorithm.

Original languageEnglish (US)
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages658-664
Number of pages7
ISBN (Electronic)9781479977925
DOIs
StatePublished - Mar 11 2015
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: Jan 19 2015Jan 22 2015

Publication series

Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period1/19/151/22/15

Fingerprint

E-beam Lithography
Optimal Algorithm
Lithography
Polynomial-time Algorithm
Planning
Polynomials
Electron Beam Lithography
Electron beam lithography
Subroutines
Integrated Circuits
NP-hard Problems
Integrated circuits
Overlapping
Computational complexity
Fabrication
Correctness
Polynomial time
Throughput
Optimal Solution
Entire

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modeling and Simulation

Cite this

Guo, D., Du, Y., & Wong, M. D. F. (2015). Polynomial time optimal algorithm for stencil row planning in e-beam lithography. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 658-664). [7059083] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059083

Polynomial time optimal algorithm for stencil row planning in e-beam lithography. / Guo, Daifeng; Du, Yuelin; Wong, Martin D F.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 658-664 7059083 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Guo, D, Du, Y & Wong, MDF 2015, Polynomial time optimal algorithm for stencil row planning in e-beam lithography. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059083, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 658-664, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 1/19/15. https://doi.org/10.1109/ASPDAC.2015.7059083
Guo D, Du Y, Wong MDF. Polynomial time optimal algorithm for stencil row planning in e-beam lithography. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 658-664. 7059083. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). https://doi.org/10.1109/ASPDAC.2015.7059083
Guo, Daifeng ; Du, Yuelin ; Wong, Martin D F. / Polynomial time optimal algorithm for stencil row planning in e-beam lithography. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 658-664 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).
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