We design new polynomials for representing threshold functions in three different regimes: probabilistic polynomials of low degree, which need far less randomness than previous constructions, polynomial threshold functions (PTFs) with 'nice' threshold behavior and degree almost as low as the probabilistic polynomials, and a new notion of probabilistic PTFs where we combine the above techniques to achieve even lower degree with similar 'nice' threshold behavior. Utilizing these polynomial constructions, we design faster algorithms for a variety of problems: Offline Hamming Nearest (and Furthest) Neighbors: Given n red and n blue points in d-dimensional Hamming space for d = c log n, we can find an (exact) nearest (or furthest) blue neighbor for every red point in randomized time n2-1/O(√c log2/3 c) or deterministic time n2-1/O(c log2 c). These improve on a randomized n2-1/O(c log2 c) bound by Alman and Williams (FOCS'15), and also lead to faster MAX-SAT algorithms for sparse CNFs. Offline Approximate Nearest (and Furthest) Neighbors: Given n red and n blue points in d-dimensional l1 or Euclidean space, we can find a (1+ϵ)-approximate nearest (or furthest) blue neighbor for each red point in randomized time near dn+n2-Ω(ϵ1/3/log(1/ϵ)). This improves on an algorithm by Valiant (FOCS'12) with randomized time near dn+n2-Ω(√ϵ), which in turn improves previous methods based on locality-sensitive hashing. SAT Algorithms and Lower Bounds for Circuits With Linear Threshold Functions: We give a satisfiability algorithm for AC0[m] ○ LTF LTF circuits with a subquadratic number of LTF gates on the bottom layer, and a subexponential number of gates on the other layers, that runs in deterministic 2n-nϵ time. This strictly generalizes a SAT algorithm for ACC0 ○ LTF circuits of subexponential size by Williams (STOC'14) and also implies new circuit lower bounds for threshold circuits, improving a recent gate lower bound of Kane and Williams (STOC'16). We also give a randomized 2n-nϵ-time SAT algorithm for subexponential-size MAJ ○ AC0 ○ LTF ○ AC0 ○ LTF circuits, where the top MAJ gate and middle LTF gates have O(n6/5-δ) fan-in.