Abstract
A novel isolation scheme named planarized trench isolation and field oxide formation using poly-silicon (PLATOP) is described. PLATOP is applicable to high-performance submicron VLSI since it results in encroachment-free shallow trenches, and planarized field oxide. The process offers poly-silicon-filled deep trenches. The process also relies on noncritical lithography and novel etch processes to planarize the deposited poly-silicon from the top of the active areas, and oxidation to consume the polysilicon in the field regions. Electrical results are presented proving the viability of the isolation scheme.
Original language | English (US) |
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Pages (from-to) | 352-354 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 17 |
Issue number | 7 |
DOIs | |
State | Published - Jul 1996 |
Externally published | Yes |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering