TY - GEN
T1 - Planar VLS grown GaAs nanowire array based HEMTs
AU - Miao, Xin
AU - Li, Xiuling
PY - 2011
Y1 - 2011
N2 - In order to suppress short channel effects as gate length of field effect transistors (FETs) continues to downscale, multi-gate FETs and nanowire FETs (NW-FETs) are poised to replace traditional planar devices. Top-down defined NW-FETs are susceptible to etching damages and the size of which is limited by lithography. Bottom-up self-assembled III-V NWs are particularly interesting because of the simplicity in processing which doesn't require lithography and chemical etching, potentially smaller feature sizes than defined by lithography and inherent high carrier mobility. However, there are three main challenges of realizing bottom-up grown NW-FET based circuits including: controllability of NW growth direction and positioning; uniformity of NW electrical property; and compatibility with planar processing.
AB - In order to suppress short channel effects as gate length of field effect transistors (FETs) continues to downscale, multi-gate FETs and nanowire FETs (NW-FETs) are poised to replace traditional planar devices. Top-down defined NW-FETs are susceptible to etching damages and the size of which is limited by lithography. Bottom-up self-assembled III-V NWs are particularly interesting because of the simplicity in processing which doesn't require lithography and chemical etching, potentially smaller feature sizes than defined by lithography and inherent high carrier mobility. However, there are three main challenges of realizing bottom-up grown NW-FET based circuits including: controllability of NW growth direction and positioning; uniformity of NW electrical property; and compatibility with planar processing.
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U2 - 10.1109/ISDRS.2011.6135169
DO - 10.1109/ISDRS.2011.6135169
M3 - Conference contribution
AN - SCOPUS:84863157591
SN - 9781457717550
T3 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
BT - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
T2 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
Y2 - 7 December 2011 through 9 December 2011
ER -