PLA Folding by Simulated Annealing

D. F. Wong; H. W. Leong; C. L. Liu

doi:10.1109/JSSC.1987.1052704

PLA Folding by Simulated Annealing

D. F. Wong, H. W. Leong, C. L. Liu

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

We present in this paper a simulated-annealing programmable-logic-array (PLA) folding algorithm for simple as well as multiple column folding. Experimental results indicate that our algorithm performs very well. In many test problems, our results are superior to those produced by the well-known heuristic algorithm due to De Micheli and Sangiovanni. We also show how our algorithm can be extended to handle constrained folding.

Original language	English (US)
Pages (from-to)	208-215
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	22
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.1987.1052704
State	Published - Apr 1987

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1987.1052704

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title = "PLA Folding by Simulated Annealing",

abstract = "We present in this paper a simulated-annealing programmable-logic-array (PLA) folding algorithm for simple as well as multiple column folding. Experimental results indicate that our algorithm performs very well. In many test problems, our results are superior to those produced by the well-known heuristic algorithm due to De Micheli and Sangiovanni. We also show how our algorithm can be extended to handle constrained folding.",

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PLA Folding by Simulated Annealing

Abstract

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