PLA Folding by Simulated Annealing

D. F. Wong, H. W. Leong, C. L. Liu

Research output: Contribution to journalArticle

Abstract

We present in this paper a simulated-annealing programmable-logic-array (PLA) folding algorithm for simple as well as multiple column folding. Experimental results indicate that our algorithm performs very well. In many test problems, our results are superior to those produced by the well-known heuristic algorithm due to De Micheli and Sangiovanni. We also show how our algorithm can be extended to handle constrained folding.

Original languageEnglish (US)
Pages (from-to)208-215
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number2
DOIs
StatePublished - Apr 1987

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Simulated annealing
Heuristic algorithms

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

PLA Folding by Simulated Annealing. / Wong, D. F.; Leong, H. W.; Liu, C. L.

In: IEEE Journal of Solid-State Circuits, Vol. 22, No. 2, 04.1987, p. 208-215.

Research output: Contribution to journalArticle

Wong, D. F. ; Leong, H. W. ; Liu, C. L. / PLA Folding by Simulated Annealing. In: IEEE Journal of Solid-State Circuits. 1987 ; Vol. 22, No. 2. pp. 208-215.
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