Pipeline template for streaming applications on heterogeneous chips

Andrés Rodrìguez, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Antonio Vilches, María Garzarán

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, we mainly focus on the API that allows the user to specify the type of parallelism exploited by each pipeline stage running on the multicore CPU, the mapping of the pipeline stages to the devices (GPU or CPU), and the number of active threads. We use a real streaming application as a case of study to illustrate the experimental results that can be obtained with this API. With this example, we evaluate how the different parameter values affect the performance and energy efficiency of a heterogenous on-chip processor (Exynos 5 Octa) that has three different computational cores: a GPU, an ARM Cortex-A15 quad-core, and an ARM Cortex-A7 quad-core.

Original languageEnglish (US)
Title of host publicationParallel Computing
Subtitle of host publicationOn the Road to Exascale
EditorsFrans Peters, Mark Parsons, Mark Sawyer, Hugh Leather, Gerhard R. Joubert
PublisherElsevier B.V.
Pages327-336
Number of pages10
ISBN (Electronic)9781614996200
DOIs
StatePublished - Jan 1 2016

Publication series

NameAdvances in Parallel Computing
Volume27
ISSN (Print)0927-5452
ISSN (Electronic)1879-808X

Keywords

  • Heterogenous chips
  • On-chip GPU
  • Parallel pipeline
  • Performance-energy efficiency

ASJC Scopus subject areas

  • Computer Science(all)

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