A high performance proportional-integral-derivative (PID) controller in a dc-dc converter requires a time optimal tuning rule. A suitable auto-tuning rule needs to perform large-signal minimum-time transient recovery, while maintaining a sufficient small-signal stability margin and closed-loop bandwidth. This paper applies a geometric approach to analytically formulate a time optimal PID controller tuning rule for a buck converter. It is shown that the proposed method achieves approximate minimum-time transient recovery in the large-signal sense. The controller gains during a small-signal transient can be shown to be representative of those obtained using a standard tuning rule. The proposed formulation closely follows the desired minimum-transient- time trajectory. This geometric representation ensures large-signal stability in a sense similar to that of sliding mode control. A buck converter prototype is tested, and the proposed scheme is implemented using the ALTERA FPGA Cyclone-II.