Physics of silicon nanodevices

For the past several decades, miniaturization in silicon integrated circuits has progressed steadily with an exponential scale described by Moore’s Law. 1 This incredible progress has generally meant that critical dimensions are reduced by a factor of two every three years, while chip density increases by a factor of four over this period. However, modern chip manufacturers have been accelerating this pace recently, and currently chips are being made with gate lengths in the 45 to 65 nm range. More scaling is expected, however, and 15-nm gate lengths are scheduled for production before the end of this decade. Such devices have been demonstrated by Intel 2 and AMD, 3 and IBM has recently shown a 6-nm gate length p-channel FET. 4 While the creation of these very small transistors is remarkable enough, the fact that they seem to operate in a quite normal fashion is perhaps even more remarkable.