Phase-locked loop simulations using the latency insertion method

Jose E Schutt-Aine, Patrick K. Goh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a novel and simple behavioral model based simulation method for PLLs. We also demonstrate the use of LIM for simulating PLLs. The methods exploit the latency in the PLL formulation and utilize a leapfrog time-stepping discretization scheme to solve for the transient response of the PLL. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Due to the formulation in the voltage-phase domain, the method does not suffer from the dual time scale problem which is a main issue in full transistor level simulations of PLLs.

Original languageEnglish (US)
Title of host publication2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
DOIs
StatePublished - 2013
Event2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Cusco, Peru
Duration: Feb 27 2013Mar 1 2013

Other

Other2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013
Country/TerritoryPeru
CityCusco
Period2/27/133/1/13

Keywords

  • Phase-locked loop (PLL)
  • simulation
  • voltage controlled oscillators

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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