TY - GEN
T1 - Phase-locked loop simulations using the latency insertion method
AU - Schutt-Aine, Jose E.
AU - Goh, Patrick K.
PY - 2013
Y1 - 2013
N2 - In this paper we present a novel and simple behavioral model based simulation method for PLLs. We also demonstrate the use of LIM for simulating PLLs. The methods exploit the latency in the PLL formulation and utilize a leapfrog time-stepping discretization scheme to solve for the transient response of the PLL. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Due to the formulation in the voltage-phase domain, the method does not suffer from the dual time scale problem which is a main issue in full transistor level simulations of PLLs.
AB - In this paper we present a novel and simple behavioral model based simulation method for PLLs. We also demonstrate the use of LIM for simulating PLLs. The methods exploit the latency in the PLL formulation and utilize a leapfrog time-stepping discretization scheme to solve for the transient response of the PLL. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Due to the formulation in the voltage-phase domain, the method does not suffer from the dual time scale problem which is a main issue in full transistor level simulations of PLLs.
KW - Phase-locked loop (PLL)
KW - simulation
KW - voltage controlled oscillators
UR - http://www.scopus.com/inward/record.url?scp=84879359893&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84879359893&partnerID=8YFLogxK
U2 - 10.1109/LASCAS.2013.6519090
DO - 10.1109/LASCAS.2013.6519090
M3 - Conference contribution
AN - SCOPUS:84879359893
SN - 9781424494859
T3 - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
BT - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
T2 - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013
Y2 - 27 February 2013 through 1 March 2013
ER -