Phase-locked loop based delta-sigma ADC

B. Young, P. K. Hanumolu

Research output: Contribution to journalArticlepeer-review


A phase-locked loop (PLL) based delta-sigma analogue-to-digital converter architecture providing second-order noise shaping is presented. By combining a low power passive integrator with a voltage-controlled oscillator-based integrator, the proposed architecture suppresses the oscillator nonlinearity with minimum hardware penalty. Simulation results indicate 14-bit performance by using only a 4-bit linear oscillator.

Original languageEnglish (US)
Pages (from-to)403-404
Number of pages2
JournalElectronics Letters
Issue number6
StatePublished - 2010
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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