Periodic steady-state analysis augmented with design equality constraints

Igor Vytyaz; Pavan Kumar Hanumolu; Un Ku Moon; Kartikeya Mayaram

doi:10.1109/DATE.2008.4484698

Periodic steady-state analysis augmented with design equality constraints

Igor Vytyaz, Pavan Kumar Hanumolu, Un Ku Moon, Kartikeya Mayaram

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

Original language	English (US)
Title of host publication	Design, Automation and Test in Europe, DATE 2008
Pages	312-317
Number of pages	6
DOIs	https://doi.org/10.1109/DATE.2008.4484698
State	Published - 2008
Externally published	Yes
Event	Design, Automation and Test in Europe, DATE 2008 - Munich, Germany Duration: Mar 10 2008 → Mar 14 2008

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)	1530-1591

Other

Other	Design, Automation and Test in Europe, DATE 2008
Country/Territory	Germany
City	Munich
Period	3/10/08 → 3/14/08

ASJC Scopus subject areas

General Engineering

Online availability

10.1109/DATE.2008.4484698

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Vytyaz, I, Hanumolu, PK, Moon, UK & Mayaram, K 2008, Periodic steady-state analysis augmented with design equality constraints. in Design, Automation and Test in Europe, DATE 2008., 4484698, Proceedings -Design, Automation and Test in Europe, DATE, pp. 312-317, Design, Automation and Test in Europe, DATE 2008, Munich, Germany, 3/10/08. https://doi.org/10.1109/DATE.2008.4484698

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author = "Igor Vytyaz and Hanumolu, {Pavan Kumar} and Moon, {Un Ku} and Kartikeya Mayaram",

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doi = "10.1109/DATE.2008.4484698",

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N2 - A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

AB - A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

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Periodic steady-state analysis augmented with design equality constraints

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