Abstract
In this paper, a pipelined strength-reduced (PIPSR) adaptive filter architecture is employed as a receive equalizer for 51.84 Mb/s ATM-LAN over unshielded twisted pair category-3 (UTP-3) wiring. This architecture provides the advantage of low-power dissipation and high-speed operation. Simulation results are presented to investigate the effect of level of pipelining on the steady-state signal-to-noise ratio at the slicer (SNRslicer). Simulation results indicate that speed-ups of up to 160 can be achieved with about 0.8 dB loss in SNRslicer.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 2132-2135 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| State | Published - 1997 |
| Event | Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: Jun 9 1997 → Jun 12 1997 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering