While multistage switching networks for vector multiprocessors have been studied extensively, detailed evaluations of their performance are rare. In this paper, an in-depth empirical analysis of a multistage switching network in a realistic setting is presented: hardware probes to examine the performance of the omega network of the Cedar shared-memory machine executing real applications is used. The analysis shows that the performance of multistage switching networks is limited by traffic non-uniformities. Hence, changes to increase the network bandwidth at the root of the traffic convergence tree and to delay traffic convergence up until the final stages of the network are suggested.
|Original language||English (US)|
|Number of pages||10|
|Journal||Proceedings of the ACM/IEEE Supercomputing Conference|
|State||Published - 1994|
ASJC Scopus subject areas
- Electrical and Electronic Engineering