As the technology advances to 14/10 nm technology nodes and beyond, multiple patterning lithography (MPL) is no longer an option but a necessity. For advanced technology nodes, process variations have significant influences on the quality of fabricated circuits, and often lead to unexpected power/timing degenerations. For example, a 6 nm misalignment causes a 15% error in coupling capacitance and a 5% error on total capacitance, whereas a 2 nm displacement creates approximately a 5% error for coupling capacitance and 2% error for total capacitance . Mask misalignment would increase the coupling capacitance for a given layout and further complicate the way of simulating timing closure. In this paper, we studied the coupling capacitance variations due to mask misalignment in MPL, and mathematically proved that worst case coupling capacitance scenarios for all MPL decompositions. Our algorithm is able to identify a decomposition with a tight upper bound on the worst case coupling capacitance, which can be used in timing/power analysis. Our approach is expected to help the engineers to quickly evaluate the quality of different decompositions, and better understand the pros and cons brought by MPL decompositions.