Performance-driven simultaneous placement and routing for FPGA's

Sudip K. Nag, Rob A. Rutenbar

Research output: Contribution to journalArticle

Abstract

Sequential place and route tools for field programmable gate arrays (FPGA's) are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A set of new performancedriven simultaneous placement/routing techniques has been developed for both row-based and island-style FPGA designs. These techniques rely on an iterative improvement placement algorithm augmented with fast complete routing heuristics in the placement loop. For row-based designs this new layout strategy yielded up to 28% improvements in timing and 33% in wirability for several MCNC benchmarks when compared to a traditional sequential place and route system in use at Texas Instruments. On a set of industrial designs for Xilinx 4000-series island-style FPGA's our scheme produced 100% routed designs with 8-15% improvement in delay when compared to the Xilinx XACT5.0 place and route system.

Original languageEnglish (US)
Pages (from-to)499-518
Number of pages20
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume17
Issue number6
DOIs
StatePublished - Dec 1 1998

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Keywords

  • Delay calculation
  • FPGA
  • Island-style
  • Placement
  • Routing
  • Row-based
  • Simulated annealing simultaneous place and route

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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