Abstract
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A new performance-driven simultaneous placement / routing technique has been developed for island-style FPGA designs. On a set of industrial designs for Xilinx 4000-series FPGAs, our scheme produces 100% routed designs with 8%-15% improvement in delay when compared to the Xilinx XACT5.0 place and route system.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 332-338 |
| Number of pages | 7 |
| Journal | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers |
| State | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA Duration: Nov 5 1995 → Nov 9 1995 |
ASJC Scopus subject areas
- Software
- Computer Science Applications
- Computer Graphics and Computer-Aided Design