Performance-driven mapping for CPLD architectures

Keyphrases

• Performance-based 100%
• Mapping Algorithm 100%
• Array Mapping 100%
• Programmable Logic Arrays 100%
• Altera 66%
• Device Architecture 33%
• Time Relaxation 33%
• Small Area 33%
• Area Reduction 33%
• Commercial Tools 33%
• Area Overhead 33%
• Benchmark Circuits 33%
• Product Terms 33%
• Circuit Depth 33%
• Threshold Control 33%
• Multiple Arrays 33%
• Logic Cell 33%
• Circuit Delay 33%
• Slack Time 33%
• Complex Programmable Logic Device 33%
• Microelectronic Center of North Carolina 33%

Computer Science

• Mapping Algorithm 100%
• Programmable Logic Array 100%
• Commercial Tool 33%
• Benchmark Circuit 33%
• Primary Objective 33%
• Programmable Logic Devices 33%
• Relaxation Time 33%