Performance-driven mapping for CPLD architectures

D. Chen, J. Cong, M. D. Ercegovac, Z. Huang

Research output: Contribution to conferencePaperpeer-review


In this paper we present a performance-driven mapping algorithm, PLAmap, for CPLD architectures which consist of a large number of PLA-style logic cells. The primary goal of our mapping algorithm is to minimize the depth of the mapped circuit. Meanwhile, we have successfully reduced the area of the mapped circuits by applying several heuristic techniques, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA-packing. We compare our PLAmap with a recently-published algorithm TEMPLA [1] and a commercial tool, Altera's MAX+PLUS II [16]. Experimental results on various MCNC benchmarks show that overall TEMPLA uses 8 to 11% less area at the cost of 96 to 106% more mapping depth, and MAX+PLUS II uses 12% less area but 58% more delay compared with our mapper.

Original languageEnglish (US)
Number of pages9
StatePublished - 2001
Externally publishedYes
Event2001 ACM/SIGDA 9th International Sysmposium on Field Programmable Gate Arrays (FPGA 2001) - Monterrey, CA, United States
Duration: Feb 11 2001Feb 13 2001


Other2001 ACM/SIGDA 9th International Sysmposium on Field Programmable Gate Arrays (FPGA 2001)
Country/TerritoryUnited States
CityMonterrey, CA


  • CPLD
  • Delay optimization
  • FPGA
  • PLA-style logic cells
  • Technology mapping

ASJC Scopus subject areas

  • General Computer Science


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