Abstract
In [9] and [10], two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.
| Original language | English (US) |
|---|---|
| Pages | 199-201 |
| Number of pages | 3 |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: Oct 5 1998 → Oct 7 1998 |
Other
| Other | Proceedings of the 1998 IEEE International Conference on Computer Design |
|---|---|
| City | Austin, TX, USA |
| Period | 10/5/98 → 10/7/98 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
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