Performance-driven board-level routing for FPGA-based logic emulation

Wai Kei Mak, Martin D F Wong

Research output: Contribution to conferencePaperpeer-review

Abstract

In [9] and [10], two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.

Original languageEnglish (US)
Pages199-201
Number of pages3
StatePublished - Dec 1 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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