Performance characterization of a hardware mechanism for dynamic optimization

Brian Fahs, Satarupa Bose, Matthew Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta

Research output: Contribution to journalArticlepeer-review


We evaluate the rePLay microarchitecture as a means for reducing application execution time by facilitating dynamic optimization. The framework contains a programmable optimization engine coupled with a hardware-based recovery mechanism. The optimization engine enables the dynamic optimizer to run concurrently with program execution. The recovery mechanism enables the optimizer to make speculative optimizations without requiring recovery code. We demonstrate that a rePLay configuration performing a small suite of simple optimizations on Alpha code attains an average of 13% reduction in execution cycles on the SPEC2000 integer benchmarks over a rePLay configuration not performing optimizations and a 21% reduction over an aggressive standard superscalar microarchitecture.

Original languageEnglish (US)
Pages (from-to)16-27
Number of pages12
JournalProceedings of the Annual International Symposium on Microarchitecture
StatePublished - Jan 1 2001

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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