Performance characteristics of strongly correlated bilayer graphene for post-CMOS logic devices

B. Dellabetta, M. J. Gilbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Post-CMOS logic in bilayer graphene is very promising due to the possibility of observing room temperature collective states. We present calculations of graphene bilayers and the conditions necessary for excitonic superfluidity. At room temperature, the maximum current the condensate can support is increased over low temperature values and we can achieve negative differential resistances greater than 3 orders of magnitude between the condensate current and the non-interacting quasiparticle current which flows after exceeding the maximum current.

Original languageEnglish (US)
Title of host publication2010 Silicon Nanoelectronics Workshop, SNW 2010
DOIs
StatePublished - Oct 22 2010
Event2010 15th Silicon Nanoelectronics Workshop, SNW 2010 - Honolulu, HI, United States
Duration: Jun 13 2010Jun 14 2010

Publication series

Name2010 Silicon Nanoelectronics Workshop, SNW 2010

Other

Other2010 15th Silicon Nanoelectronics Workshop, SNW 2010
CountryUnited States
CityHonolulu, HI
Period6/13/106/14/10

Keywords

  • Graphene
  • Logic
  • Post-CMOS
  • Simulation
  • Transport

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Performance characteristics of strongly correlated bilayer graphene for post-CMOS logic devices'. Together they form a unique fingerprint.

  • Cite this

    Dellabetta, B., & Gilbert, M. J. (2010). Performance characteristics of strongly correlated bilayer graphene for post-CMOS logic devices. In 2010 Silicon Nanoelectronics Workshop, SNW 2010 [5562544] (2010 Silicon Nanoelectronics Workshop, SNW 2010). https://doi.org/10.1109/SNW.2010.5562544