Performance analysis and tuning for general purpose graphics processing units (GPGPU)

Hyesoon Kim, Richard Vuduc, Sara Baghsorkhi, Wen Mei Hwu, Choi Jee Choi

Research output: Chapter in Book/Report/Conference proceedingChapter


General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Relative to more traditional multicore systems of today, GPGPUs have distinctly higher degrees of hardware multithreading (hundreds of hardware thread contexts vs. tens), a return to wide vector units (several tens vs. 1-10), memory architectures that deliver higher peak memory bandwidth (hundreds of gigabytes per second vs. tens), and smaller caches/scratchpad memories (less than 1 megabyte vs. 1-10 megabytes). In this book, we provide a high-level overview of current GPGPU architectures and programming models.We review the principles that are used in previous shared memory parallel platforms, focusing on recent results in both the theory and practice of parallel algorithms, and suggest a connection to GPGPU platforms.We aim to provide hints to architects about understanding algorithm aspect to GPGPU. We also provide detailed performance analysis and guide optimizations from high-level algorithms to low-level instruction level optimizations. As a case study, we use n-body particle simulations known as the fast multipole method (FMM) as an example. We also briefly survey the state-of-the-art in GPU performance analysis tools and techniques.

Original languageEnglish (US)
Title of host publicationPerformance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)
Number of pages94
StatePublished - Nov 21 2012

Publication series

NameSynthesis Lectures on Computer Architecture
ISSN (Print)1935-3235
ISSN (Electronic)1935-3243


  • CUDA
  • GPU
  • performance analysis
  • performance modeling

ASJC Scopus subject areas

  • Hardware and Architecture

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