Pareto optimal modeling for efficient PLL optimization

Saurabh Kumar Tiwary, Senthil Velu, Rob A. Rutenbar, Tamal Mukherjee

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each complete circuit solution candidate is prohibitive inside a numerical optimization loop. In this paper, we show how to circumvent this problem with a careful mix of behavioral models for less-critical parts of the block, and pareto-optimal trade-off models for the critical components. In particular, we show how to adapt current circuit synthesis techniques to build the required tradeoff models. As a concrete example of the methodology, we show detailed simulation results from the synthesis of critical portions of a 500MHz digital frequency synthesizer PLL.

Original languageEnglish (US)
Title of host publication2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
EditorsM. Laudon, B. Romanowicz
Number of pages4
StatePublished - 2004
Externally publishedYes
Event2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States
Duration: Mar 7 2004Mar 11 2004


Other2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Country/TerritoryUnited States
CityBoston, MA


  • Analog circuits
  • Behavioral modeling
  • Circuit optimization
  • Pareto-optimal design
  • Phase locked-loop

ASJC Scopus subject areas

  • Engineering(all)


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