Abstract
In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential. Fast algorithms, such as the multipole or precorrected Fast Fourier Transform (FFT) accelerated methods in programs like FASTCAP, must be combined with techniques to exploit the emerging cluster-of-workstation based parallel computers like the IBM SP2. In this paper, we examine parallelizing the precorrected FFT algorithm for 3-D capacitance extraction and present several algorithms for balancing workload and reducing communication time. Results from a prototype implementation on an eight processor IBM SP2 are presented for several test examples, and the largest of these examples achieves nearly linear parallel speed-up.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 363-366 |
| Number of pages | 4 |
| Journal | Proceedings - Design Automation Conference |
| State | Published - 1996 |
| Externally published | Yes |
| Event | Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA Duration: Jun 3 1996 → Jun 7 1996 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering