@inproceedings{db33b035218546bbb9afe0fe1ee1de8d,
title = "Parallel Pipeline on Heterogeneous Multi-processing Architectures",
abstract = "We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, we present an API that allows the user to specify the type of parallelism exploited by each pipeline stage running on the CPU multicore, the mapping of the pipeline stages to the devices (GPU or CPU), and the number of active threads. Using as case of study a real streaming application, we evaluate how these parameters affect the performance and energy efficiency of a heterogeneous on-chip processor (Exynos 5 Octa) that has three different computational cores: a GPU, an A15 quad-core and an A7 quad-core. We also explore some memory optimizations and find that while their performance impact depends on the granularity type, they usually reduce energy consumption.",
keywords = "Heterogeneous chips, On-chip GPU, Performance-Energy efficiency, Pipeline pattern",
author = "Andres Rodriguez and Angeles Navarro and Rafael Asenjo and Antonio Vilches and Francisco Corbera and Maria Garzaran",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 14th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2015 ; Conference date: 20-08-2015 Through 22-08-2015",
year = "2015",
month = dec,
day = "2",
doi = "10.1109/Trustcom.2015.627",
language = "English (US)",
series = "Proceedings - 14th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "166--171",
booktitle = "Proceedings - 13th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2015",
address = "United States",
}