Parallel Implementation of A 4 4-Bit Multiplier Using Modified Booth'S Algorithm

Naresh R. Shanbhag, Pushkal Juneja

Research output: Contribution to journalArticlepeer-review

Abstract

Presented in this paper is a design of a 4 4-bit multiplier using the modified Booth's algorithm in 2-üm NMOS technology. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm2. A novel adder-cum-subtractor (ACS) circuit was designed to realize the arithmetic processing part.

Original languageEnglish (US)
Pages (from-to)1010-1013
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume23
Issue number4
DOIs
StatePublished - Aug 1988
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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