Abstract
Presented in this paper is a design of a 4 4-bit multiplier using the modified Booth's algorithm in 2-üm NMOS technology. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm2. A novel adder-cum-subtractor (ACS) circuit was designed to realize the arithmetic processing part.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1010-1013 |
| Number of pages | 4 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 23 |
| Issue number | 4 |
| DOIs | |
| State | Published - Aug 1988 |
| Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering