Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design

Keyphrases

• Source Code 100%
• Dynamic Phase 100%
• Latency 100%
• Parallel Code 100%
• Sniper 100%
• HW-SW Co-design 100%
• Gem5 100%
• TLM-2.0 100%
• SystemC Modeling 66%
• Parallelizing 33%
• Dynamic Steady State 33%
• Level Energies 33%
• Performance Data 33%
• System-on-chip 33%
• Energy Data 33%
• State Phase 33%
• Promising Solutions 33%
• Code Generation 33%
• Detailed Annotation 33%
• C++ Code 33%
• Transaction-level 33%
• Automated Framework 33%
• Automatic Annotation 33%
• Virtual Prototyping 33%
• Code Profiling 33%
• SystemC TLM 33%

Computer Science

• Participatory Design 100%
• SystemC 100%
• Source Codes 60%
• Average Accuracy 40%
• Performance Data 20%
• Annotation 20%
• Code Generation 20%
• System-on-Chip 20%
• Automatic Annotation 20%
• Level Transaction 20%
• Average Result 20%
• Target Processor 20%
• Virtual Prototype 20%
• Code Profiling 20%