Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking

Brian Greskamp, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost performance and improve single-thread performance, this paper presents the Paceline leader-checker microarchitecture. In Paceline, a leader core runs the thread at higher-than-rated frequency, while passing execution hints and prefetches to a safely-clocked checker core in the same chip multiprocessor. The checker redundantly executes the thread faster than without the leader, while checking the results to guarantee correctness. Leader and checker cores periodically swap functionality. The result is that the thread improves performance substantially without significantly increasing the power density or the hardware design complexity of the chip. By overclocking the leader by 30%, we estimate that Paceline improves SPECint and SPECfp performance by a geometric mean of 21% and 9%, respectively. Moreover, Paceline also provides tolerance to transient faults such as soft errors.

Original languageEnglish (US)
Title of host publication16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
Pages213-224
Number of pages12
DOIs
StatePublished - Dec 1 2007
Event16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 - Brasov, Romania
Duration: Sep 15 2007Sep 19 2007

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Conference

Conference16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
CountryRomania
CityBrasov
Period9/15/079/19/07

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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