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OUTRIDER: Efficient memory latency tolerance with decoupled strands
Neal C. Crago
,
Sanjay J. Patel
Electrical and Computer Engineering
Information Trust Institute
Coordinated Science Lab
European Union Center
Office of the Provost and Executive Vice Chancellor
Siebel School of Computing and Data Science
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Dive into the research topics of 'OUTRIDER: Efficient memory latency tolerance with decoupled strands'. Together they form a unique fingerprint.
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Keyphrases
Single Thread
100%
Instruction Stream
100%
Memory Latency Tolerance
100%
Memory Latency
100%
Microarchitecture
50%
Performance Improvement
50%
Performance Gain
50%
Data-parallel Applications
50%
Core System
50%
In-order
50%
Out-of-order
50%
Processor Pipeline
50%
Area-efficient
50%
4-way
50%
Hardware Thread
50%
Simultaneous multithreaded
50%
Computer Science
Memory Latency
100%
Instruction Stream
50%
Microarchitecture
25%
Parallel Application
25%
Performance Gain
25%
Shared Resource
25%
Pipeline Processor
25%
Accessing Memory
25%
Hardware Thread
25%
Graphics Processing Unit
25%