OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Sergi Abadal, Josep Torrellas, Eduard Alarcon, Albert Cabellos-Aparicio

Research output: Contribution to journalArticlepeer-review


On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents OrthoNoC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, OrthoNoC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of OrthoNoC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of OrthoNoC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of OrthoNoC goes beyond simply improving the performance of the on-chip interconnect.

Original languageEnglish (US)
Article number8078211
Pages (from-to)628-641
Number of pages14
JournalIEEE Transactions on Parallel and Distributed Systems
Issue number3
StatePublished - Mar 1 2018


  • Network-on-Chip
  • broadcast
  • hybrid NoC
  • manycore processors
  • wireless on-chip communication

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics

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