Optimum design for a two-stage CMOS I/O ESD protection circuit

Tong Li, P. Bendix, D. Suh, Y. J. Huh, E. Rosenbaum, A. Kapoor, S. M. Kang

Research output: Contribution to journalConference article

Abstract

In industry, the design of CMOS ESD (electro-static discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.

Original languageEnglish (US)
Pages (from-to)113-116
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

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Resistors
Networks (circuits)
Optimum design
Industry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Optimum design for a two-stage CMOS I/O ESD protection circuit. / Li, Tong; Bendix, P.; Suh, D.; Huh, Y. J.; Rosenbaum, E.; Kapoor, A.; Kang, S. M.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1998, p. 113-116.

Research output: Contribution to journalConference article

Li, Tong ; Bendix, P. ; Suh, D. ; Huh, Y. J. ; Rosenbaum, E. ; Kapoor, A. ; Kang, S. M. / Optimum design for a two-stage CMOS I/O ESD protection circuit. In: Proceedings - IEEE International Symposium on Circuits and Systems. 1998 ; Vol. 2. pp. 113-116.
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