Optimum design for a two-stage CMOS I/O ESD protection circuit

Tong Li; P. Bendix; D. Suh; Y. J. Huh; E. Rosenbaum; A. Kapoor; S. M. Kang

Optimum design for a two-stage CMOS I/O ESD protection circuit

Tong Li, P. Bendix, D. Suh, Y. J. Huh, E. Rosenbaum, A. Kapoor, S. M. Kang

Research output: Contribution to journal › Conference article › peer-review

Abstract

In industry, the design of CMOS ESD (electro-static discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.

Original language	English (US)
Pages (from-to)	113-116
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
State	Published - 1998
Event	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: May 31 1998 → Jun 3 1998

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Electrical and Electronic Engineering

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title = "Optimum design for a two-stage CMOS I/O ESD protection circuit",

abstract = "In industry, the design of CMOS ESD (electro-static discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.",

author = "Tong Li and P. Bendix and D. Suh and Huh, {Y. J.} and E. Rosenbaum and A. Kapoor and Kang, {S. M.}",

year = "1998",

language = "English (US)",

volume = "2",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) ; Conference date: 31-05-1998 Through 03-06-1998",

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TY - JOUR

T1 - Optimum design for a two-stage CMOS I/O ESD protection circuit

AU - Li, Tong

AU - Bendix, P.

AU - Suh, D.

AU - Huh, Y. J.

AU - Rosenbaum, E.

AU - Kapoor, A.

AU - Kang, S. M.

PY - 1998

Y1 - 1998

N2 - In industry, the design of CMOS ESD (electro-static discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.

AB - In industry, the design of CMOS ESD (electro-static discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.

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M3 - Conference article

AN - SCOPUS:0031622748

SN - 0271-4310

VL - 2

SP - 113

EP - 116

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)

Y2 - 31 May 1998 through 3 June 1998

ER -

Optimum design for a two-stage CMOS I/O ESD protection circuit

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