Optimizing total power of many-core processors considering voltage scaling limit and process variations

Jungseob Lee, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently, processor manufacturers have integrated more than a hundred cores in a single die to deliver extremely high throughput for highly-parallel, data-intensive applications like physics simulations, 3D-graphics, etc. Meanwhile, excessive power consumption rather than silicon area will limit the performance of many-core processors running the aforementioned applications. In this paper, to optimize the total power of many-core processors, we analyze the impact of 1) the number of cores, 2) parallelism in applications, and 3) supply voltage scaling limit due to on-die memory failure at low supply voltage. Our analysis shows that doubling the number of cores with lower than nominal supply voltage offers the most cost-effective power reduction, resulting in up to 65% less power consumption for highly-parallel applications even when supply voltage scaling is limited to 0.7V. The reduced power, in turn, can be used to improve throughput at higher voltage in power-constrained many-core processors. Furthermore, we extend our analysis to consider within-die core-to-core frequency and leakage variations. When only a subset of cores in a many-core processor are to be chosen to achieve a demanded throughput, moderately fast and leaky cores always provide optimal power consumption. In addition, frequency-island clocking, which allows independent frequency for each core, leads to ∼7% less power consumption than global clocking, and it prefers the fastest core (among the chosen ones) to process the totally sequential portion of workload.

Original languageEnglish (US)
Title of host publicationISLPED'09 - Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design
Pages201-206
Number of pages6
DOIs
StatePublished - Nov 24 2009
Event2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09 - San Fancisco, CA, United States
Duration: Aug 19 2009Aug 21 2009

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09
CountryUnited States
CitySan Fancisco, CA
Period8/19/098/21/09

Keywords

  • Many-core processor
  • Parallel applications
  • Process variations
  • Voltage and frequency scaling

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Lee, J., & Kim, N. S. (2009). Optimizing total power of many-core processors considering voltage scaling limit and process variations. In ISLPED'09 - Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design (pp. 201-206). [1594283] (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1594233.1594283