@inproceedings{1a1eba98589b47b6b3c229e849887ee8,
title = "Optimizing matrix transposes using a POWER7 cache model and explicit prefetching",
abstract = "We develop a matrix transpose approach on the POWER7 architecture based on modeling the memory access latency and cache, and then designing the cache blocking, data alignment, and prefetching techniques that enhance performance.",
keywords = "Cache, Matrix transpose, POWER7, Prefetching",
author = "Gabriel Mateescu and Bauer, {Gregory H.} and Fiedler, {Robert A.}",
year = "2011",
doi = "10.1145/2088457.2088461",
language = "English (US)",
isbn = "9781450311021",
series = "PMBS'11 - Proceedings of the 2nd International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems, Co-located with SC'11",
pages = "5--6",
booktitle = "PMBS'11 - Proceedings of the 2nd International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems, Co-located with SC'11",
note = "2nd Int. Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems, PMBS'11, Held as Part of the 24th ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, SC'11 ; Conference date: 13-11-2011 Through 13-11-2011",
}