TY - GEN
T1 - Optimizing ASCON Permutation in Multi-Clock Domains with Chisel
T2 - 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
AU - El-Hadedy, Mohamed
AU - Hua, Russell
AU - Yoshii, Kazutomo
AU - Hwu, Wen Mei
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This study delves into optimizing the ASCON cryptographic protocol, specifically its core permutation function critical for the sponge-construction mechanism, within Field Programmable Gate Array (FPGA) platforms to enhance Internet of Things (IoT) device security. By implementing a novel approach that marries multi-clock domain strategies with pipelining, we substantially elevate the permutation function's efficiency and operational frequency. Our FPGA-based ASCON IP showcases an operational frequency of 233.3MHz, leveraging the distinct advantages of multi-clock domains to mitigate inherent hardware resource constraints and achieve reasonable performance despite Application Specific Integrated Circuits (ASIC)s traditionally reaching higher frequencies up to 633MHz. Notably, the architecture's innovative division into two stages-first, integrating the add constant and substitution and second, concentrating on the diffusion layer-enables optimized processing speeds by allowing each stage to function at its maximum effective clock rate, thereby enhancing overall throughput. The first stage achieves a remarkable frequency of up to 465 MHz, utilizing 210 Look-Up Table (LUTs), 362 Flip-Flops (FF)s, and 0.5 Block RAM (BRAM), while the second stage operates up to 233 MHz with 848 LUTs and 623 FFs. This strategic configuration, supported by a double-rating buffer, ensures seamless data flow between stages, significantly improving the permutation process's efficiency. The proposed design, meticulously developed in Chisel, exemplifies how integrating high-level programming agility with precise hardware control can spur innovation in cryptographic hardware design, propelling the development process forward without compromising on performance or security. Through this advanced approach, we set a new benchmark for implementing lightweight, high-performance cryptographic solutions, aiming to secure the proliferating IoT ecosystem effectively.
AB - This study delves into optimizing the ASCON cryptographic protocol, specifically its core permutation function critical for the sponge-construction mechanism, within Field Programmable Gate Array (FPGA) platforms to enhance Internet of Things (IoT) device security. By implementing a novel approach that marries multi-clock domain strategies with pipelining, we substantially elevate the permutation function's efficiency and operational frequency. Our FPGA-based ASCON IP showcases an operational frequency of 233.3MHz, leveraging the distinct advantages of multi-clock domains to mitigate inherent hardware resource constraints and achieve reasonable performance despite Application Specific Integrated Circuits (ASIC)s traditionally reaching higher frequencies up to 633MHz. Notably, the architecture's innovative division into two stages-first, integrating the add constant and substitution and second, concentrating on the diffusion layer-enables optimized processing speeds by allowing each stage to function at its maximum effective clock rate, thereby enhancing overall throughput. The first stage achieves a remarkable frequency of up to 465 MHz, utilizing 210 Look-Up Table (LUTs), 362 Flip-Flops (FF)s, and 0.5 Block RAM (BRAM), while the second stage operates up to 233 MHz with 848 LUTs and 623 FFs. This strategic configuration, supported by a double-rating buffer, ensures seamless data flow between stages, significantly improving the permutation process's efficiency. The proposed design, meticulously developed in Chisel, exemplifies how integrating high-level programming agility with precise hardware control can spur innovation in cryptographic hardware design, propelling the development process forward without compromising on performance or security. Through this advanced approach, we set a new benchmark for implementing lightweight, high-performance cryptographic solutions, aiming to secure the proliferating IoT ecosystem effectively.
KW - ASCON
KW - AXI
KW - Chisel
KW - FPGA
KW - IoT
KW - Lightweight Cryptography
KW - MicroBlaze
KW - Verilog
UR - http://www.scopus.com/inward/record.url?scp=85195467083&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85195467083&partnerID=8YFLogxK
U2 - 10.1109/DCAS61159.2024.10539908
DO - 10.1109/DCAS61159.2024.10539908
M3 - Conference contribution
AN - SCOPUS:85195467083
T3 - Proceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
BT - Proceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 19 April 2024 through 21 April 2024
ER -