Optimizing ASCON Permutation in Multi-Clock Domains with Chisel: Resource Efficiency and Critical Path Reduction

Mohamed El-Hadedy, Russell Hua, Kazutomo Yoshii, Wen Mei Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This study delves into optimizing the ASCON cryptographic protocol, specifically its core permutation function critical for the sponge-construction mechanism, within Field Programmable Gate Array (FPGA) platforms to enhance Internet of Things (IoT) device security. By implementing a novel approach that marries multi-clock domain strategies with pipelining, we substantially elevate the permutation function's efficiency and operational frequency. Our FPGA-based ASCON IP showcases an operational frequency of 233.3MHz, leveraging the distinct advantages of multi-clock domains to mitigate inherent hardware resource constraints and achieve reasonable performance despite Application Specific Integrated Circuits (ASIC)s traditionally reaching higher frequencies up to 633MHz. Notably, the architecture's innovative division into two stages-first, integrating the add constant and substitution and second, concentrating on the diffusion layer-enables optimized processing speeds by allowing each stage to function at its maximum effective clock rate, thereby enhancing overall throughput. The first stage achieves a remarkable frequency of up to 465 MHz, utilizing 210 Look-Up Table (LUTs), 362 Flip-Flops (FF)s, and 0.5 Block RAM (BRAM), while the second stage operates up to 233 MHz with 848 LUTs and 623 FFs. This strategic configuration, supported by a double-rating buffer, ensures seamless data flow between stages, significantly improving the permutation process's efficiency. The proposed design, meticulously developed in Chisel, exemplifies how integrating high-level programming agility with precise hardware control can spur innovation in cryptographic hardware design, propelling the development process forward without compromising on performance or security. Through this advanced approach, we set a new benchmark for implementing lightweight, high-performance cryptographic solutions, aiming to secure the proliferating IoT ecosystem effectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350349535
DOIs
StatePublished - 2024
Externally publishedYes
Event17th IEEE Dallas Circuits and Systems Conference, DCAS 2024 - Hybrid, Dallas, United States
Duration: Apr 19 2024Apr 21 2024

Publication series

NameProceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024

Conference

Conference17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
Country/TerritoryUnited States
CityHybrid, Dallas
Period4/19/244/21/24

Keywords

  • ASCON
  • AXI
  • Chisel
  • FPGA
  • IoT
  • Lightweight Cryptography
  • MicroBlaze
  • Verilog

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Modeling and Simulation

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