Optimized CDM-ESD Protection for 100+ Gbps Wireline IO in 16-nm CMOS

Shudong Huang, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents an ESD solution for high-speed serial IO pins, in which a STI-poly-bounded silicon-controlled rectifier (SCR) is integrated into an impedance matching circuit. The proposed all-pass secondary protection network provides excellent voltage clamping under CDM-like conditions, resulting in a peak voltage of just 2 V in response to 5-A 1-ns VFTLP current injection. Integrated with a T-coil circuit, the network achieves a bandwidth above 40 GHz, as well as broadband impedance matching.

Original languageEnglish (US)
Title of host publication2025 IEEE International Reliability Physics Symposium, IRPS 2025 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331504779
DOIs
StatePublished - 2025
Event2025 IEEE International Reliability Physics Symposium, IRPS 2025 - Monterey, United States
Duration: Mar 30 2025Apr 3 2025

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2025 IEEE International Reliability Physics Symposium, IRPS 2025
Country/TerritoryUnited States
CityMonterey
Period3/30/254/3/25

Keywords

  • electrostatic discharge (ESD)
  • FinFET
  • silicon controlled rectifier (SCR)

ASJC Scopus subject areas

  • General Engineering

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