Optimization of standard cell based detailed placement for 16 nm FinFET process

Yuelin Du, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

FinFET transistors have great advantages over traditional planar MOSFET transistors in high performance and low power applications. Major foundries are adopting the Fin-FET technology for CMOS semiconductor device fabrication in the 16 nm technology node and beyond. Edge device degradation is among the major challenges for the FinFET process. To avoid such degradation, dummy gates are needed on device edges, and the dummy gates have to be tied to power rails in order not to introduce unconnected parasitic transistors. This requires that each dummy gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which costs more placement area. Usually there is some flexibility during detailed placement to horizontally flip the cells or switch the positions of adjacent cells, which has little impact on the global placement objectives, such as timing conditions and net congestion. This paper proposes a detailed placement optimization strategy for the standard cell based designs. By flipping a subset of cells in a standard cell row and switching pairs of adjacent cells, the number of drain to drain abutments between adjacent cell boundaries can be optimally minimized, which saves additional source node insertion and reduces the length of the standard cell row. In addition, the proposed graph model can be easily modified to consider more complicated design rules. The experimental results show that the optimization of 100k cells is completed within 0.1 second, verifying the efficiency of the proposed algorithm.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
StatePublished - Jan 1 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: Mar 24 2014Mar 28 2014

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period3/24/143/28/14

Fingerprint

Transistors
Degradation
Foundries
Semiconductor devices
Field effect transistors
Rails
Switches
Fabrication
FinFET
Costs

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Du, Y., & Wong, M. D. F. (2014). Optimization of standard cell based detailed placement for 16 nm FinFET process. In Proceedings - Design, Automation and Test in Europe, DATE 2014 [6800571] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/DATE2014.370

Optimization of standard cell based detailed placement for 16 nm FinFET process. / Du, Yuelin; Wong, Martin D F.

Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6800571 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Du, Y & Wong, MDF 2014, Optimization of standard cell based detailed placement for 16 nm FinFET process. in Proceedings - Design, Automation and Test in Europe, DATE 2014., 6800571, Proceedings -Design, Automation and Test in Europe, DATE, Institute of Electrical and Electronics Engineers Inc., 17th Design, Automation and Test in Europe, DATE 2014, Dresden, Germany, 3/24/14. https://doi.org/10.7873/DATE2014.370
Du Y, Wong MDF. Optimization of standard cell based detailed placement for 16 nm FinFET process. In Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6800571. (Proceedings -Design, Automation and Test in Europe, DATE). https://doi.org/10.7873/DATE2014.370
Du, Yuelin ; Wong, Martin D F. / Optimization of standard cell based detailed placement for 16 nm FinFET process. Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings -Design, Automation and Test in Europe, DATE).
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