TY - GEN
T1 - Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology
AU - Huang, Shudong
AU - Parthasarathy, Srivatsan
AU - Zhou, Yuanzhong Paul
AU - Hajjar, Jean Jacques
AU - Rosenbaum, Elyse
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This work presents a low-leakage silicon-controlled-rectifier (SCR) for ESD protection in a 45-nm PDSOI CMOS technology. The newly proposed trigger circuit utilizes a gate-coupled NMOS to provide a low trigger voltage, making the SCR suitable for gate oxide protection. Reverse body bias is used to achieve a low DC leakage current. The anode-cathode spacing of the SCR is optimized to provide a low overshoot voltage while avoiding punchthrough. the optimized SCR shows up to 50% improvement in voltage overshoot during very fast transients on the CDM timescale.
AB - This work presents a low-leakage silicon-controlled-rectifier (SCR) for ESD protection in a 45-nm PDSOI CMOS technology. The newly proposed trigger circuit utilizes a gate-coupled NMOS to provide a low trigger voltage, making the SCR suitable for gate oxide protection. Reverse body bias is used to achieve a low DC leakage current. The anode-cathode spacing of the SCR is optimized to provide a low overshoot voltage while avoiding punchthrough. the optimized SCR shows up to 50% improvement in voltage overshoot during very fast transients on the CDM timescale.
KW - CMOS
KW - SCR
KW - SOI
KW - electrostatic discharge
UR - http://www.scopus.com/inward/record.url?scp=85160439623&partnerID=8YFLogxK
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U2 - 10.1109/IRPS48203.2023.10118266
DO - 10.1109/IRPS48203.2023.10118266
M3 - Conference contribution
AN - SCOPUS:85160439623
T3 - IEEE International Reliability Physics Symposium Proceedings
BT - 2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Reliability Physics Symposium, IRPS 2023
Y2 - 26 March 2023 through 30 March 2023
ER -