Optimization of machine descriptions for efficient use

John C. Gyllenhaal, Wen mei W. Hwu, B. Ramakrishna Rau

Research output: Contribution to journalConference article

Abstract

A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation, This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, Sun Super-SPARC, and AMD-K5 processors are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.

Original languageEnglish (US)
Pages (from-to)349-358
Number of pages10
JournalProceedings of the Annual International Symposium on Microarchitecture
StatePublished - Dec 1 1996
EventProceedings of the 1996 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-29 - Paris, Fr
Duration: Dec 2 1996Dec 4 1996

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High level languages
Sun
Scheduling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Optimization of machine descriptions for efficient use. / Gyllenhaal, John C.; Hwu, Wen mei W.; Rau, B. Ramakrishna.

In: Proceedings of the Annual International Symposium on Microarchitecture, 01.12.1996, p. 349-358.

Research output: Contribution to journalConference article

@article{6b59023120784e3894e1680cdf77eb68,
title = "Optimization of machine descriptions for efficient use",
abstract = "A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation, This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, Sun Super-SPARC, and AMD-K5 processors are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.",
author = "Gyllenhaal, {John C.} and Hwu, {Wen mei W.} and Rau, {B. Ramakrishna}",
year = "1996",
month = "12",
day = "1",
language = "English (US)",
pages = "349--358",
journal = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
issn = "1072-4451",

}

TY - JOUR

T1 - Optimization of machine descriptions for efficient use

AU - Gyllenhaal, John C.

AU - Hwu, Wen mei W.

AU - Rau, B. Ramakrishna

PY - 1996/12/1

Y1 - 1996/12/1

N2 - A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation, This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, Sun Super-SPARC, and AMD-K5 processors are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.

AB - A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation, This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, Sun Super-SPARC, and AMD-K5 processors are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.

UR - http://www.scopus.com/inward/record.url?scp=0030420465&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030420465&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030420465

SP - 349

EP - 358

JO - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

JF - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

SN - 1072-4451

ER -