Abstract
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation. This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, SUN SuperSPARC, and AMD-K5 processors, as well as two hypothetical wider-issue processor configurations, are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 417-447 |
| Number of pages | 31 |
| Journal | International Journal of Parallel Programming |
| Volume | 26 |
| Issue number | 4 |
| DOIs | |
| State | Published - Jan 1 1998 |
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Keywords
- Compiler optimization
- Instruction scheduling
- Machine description
- Pipeline resource hazard
- Reservation tables
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Information Systems
Cite this
Optimization of Machine Descriptions for Efficient Use. / Gyllenhaal, John C.; Hwu, Wen-Mei W; Rau, B. Ramakrishna.
In: International Journal of Parallel Programming, Vol. 26, No. 4, 01.01.1998, p. 417-447.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Optimization of Machine Descriptions for Efficient Use
AU - Gyllenhaal, John C.
AU - Hwu, Wen-Mei W
AU - Rau, B. Ramakrishna
PY - 1998/1/1
Y1 - 1998/1/1
N2 - A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation. This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, SUN SuperSPARC, and AMD-K5 processors, as well as two hypothetical wider-issue processor configurations, are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.
AB - A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation. This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient low-level representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, SUN SuperSPARC, and AMD-K5 processors, as well as two hypothetical wider-issue processor configurations, are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.
KW - Compiler optimization
KW - Instruction scheduling
KW - Machine description
KW - Pipeline resource hazard
KW - Reservation tables
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U2 - 10.1023/A:1018750515365
DO - 10.1023/A:1018750515365
M3 - Article
AN - SCOPUS:0032140112
VL - 26
SP - 417
EP - 447
JO - International Journal of Parallel Programming
JF - International Journal of Parallel Programming
SN - 0885-7458
IS - 4
ER -