TY - GEN
T1 - Optimal relaxation of I/O electrical requirements under packaging uncertainty by stochastic methods
AU - Chen, Xu
AU - Ochoa, Juan S.
AU - Schutt-Aine, Jose E.
AU - Cangellaris, Andreas C.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/11
Y1 - 2014/9/11
N2 - Fast and accurate evaluation of system failure rate is performed using stochastic collocation methods. First, we demonstrate that variability in I/O performance, such as driven voltage and slew rate, will impact failure probability of the link. For instance, higher slew rates will lead to increased levels of crosstalk between signals. Crosstalk above a certain threshold can be an indicator of system failure. Then, we demonstrate that by defining an upper bound for failure probability, an optimally relaxed set of I/O performance metrics can be generated corresponding to a stochastic interconnect model. This can be achieved by minimizing a cost function formulated with some performance metric, if these metrics are random variables. Lastly, we demonstrate that, if more information about the packaging design becomes available, the randomness of the interconnect model can be reduced, leading to a more relaxed set of I/O performance metrics. The method proposed in [1] is then be used to verify that the packaging design will meet the tolerated failure probability.
AB - Fast and accurate evaluation of system failure rate is performed using stochastic collocation methods. First, we demonstrate that variability in I/O performance, such as driven voltage and slew rate, will impact failure probability of the link. For instance, higher slew rates will lead to increased levels of crosstalk between signals. Crosstalk above a certain threshold can be an indicator of system failure. Then, we demonstrate that by defining an upper bound for failure probability, an optimally relaxed set of I/O performance metrics can be generated corresponding to a stochastic interconnect model. This can be achieved by minimizing a cost function formulated with some performance metric, if these metrics are random variables. Lastly, we demonstrate that, if more information about the packaging design becomes available, the randomness of the interconnect model can be reduced, leading to a more relaxed set of I/O performance metrics. The method proposed in [1] is then be used to verify that the packaging design will meet the tolerated failure probability.
UR - http://www.scopus.com/inward/record.url?scp=84907886511&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84907886511&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2014.6897363
DO - 10.1109/ECTC.2014.6897363
M3 - Conference contribution
AN - SCOPUS:84907886511
T3 - Proceedings - Electronic Components and Technology Conference
SP - 717
EP - 722
BT - Proceedings - Electronic Components and Technology Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th Electronic Components and Technology Conference, ECTC 2014
Y2 - 27 May 2014 through 30 May 2014
ER -