TY - GEN
T1 - Optimal redistribution of white space for wire length minimization
AU - Tang, Xiaoping
AU - Tian, Ruiqi
AU - Wong, Martin D.F.
PY - 2005
Y1 - 2005
N2 - Existing floorplainning algorithms compact blocks to the left ancl bottom. Although the compaction obtains an optimal area, it may not be good to meet other objectives such as minimizing total wire length which is the first-order objective. It is not known in the literature how to place blocks to obtain an optimal wire length. In this paper, we first show that the problem can be formulated as linear programming. Thereafter, instead of using the general but slow linear programming, we propose an efficient min-cost flow based approach to solve it. Our approach guarantees to obtain he minimum of total wire length in polynomial time and meanwhile keep the minimum area by distributing white space smarter for a given floorplan topology. We also show that the approach can be easily extended to handle constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, soft blocks, one-dimensional cluster placement, and bounded net delay, without loss of optimality. Practically, the algorithm is so efficient in that it finishes in less than 0.4 seconds for all MCNC benchmarks of block placement. It is also very effective. Experimental results show we can improve 4.2% of wire length even on very compact floorplans. Thus it provides an ideal way of post-floorplanning (refine floorplanning).
AB - Existing floorplainning algorithms compact blocks to the left ancl bottom. Although the compaction obtains an optimal area, it may not be good to meet other objectives such as minimizing total wire length which is the first-order objective. It is not known in the literature how to place blocks to obtain an optimal wire length. In this paper, we first show that the problem can be formulated as linear programming. Thereafter, instead of using the general but slow linear programming, we propose an efficient min-cost flow based approach to solve it. Our approach guarantees to obtain he minimum of total wire length in polynomial time and meanwhile keep the minimum area by distributing white space smarter for a given floorplan topology. We also show that the approach can be easily extended to handle constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, soft blocks, one-dimensional cluster placement, and bounded net delay, without loss of optimality. Practically, the algorithm is so efficient in that it finishes in less than 0.4 seconds for all MCNC benchmarks of block placement. It is also very effective. Experimental results show we can improve 4.2% of wire length even on very compact floorplans. Thus it provides an ideal way of post-floorplanning (refine floorplanning).
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U2 - 10.1145/1120725.1120900
DO - 10.1145/1120725.1120900
M3 - Conference contribution
AN - SCOPUS:54549110399
SN - 0780387368
SN - 9780780387362
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 412
EP - 417
BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Y2 - 18 January 2005 through 21 January 2005
ER -