Optimal power/Performance pipelining for error resilient processors

Nicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Timing speculation has been proposed as a technique for maximizing the energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation involves speculatively reducing the voltage of a processor to a point where errors are possible but rare, and employing an error recovery mechanism to ensure correct functionality. This allows significant energy savings with a small recovery overhead. Previous work on timing speculation has either explored the benefits of customizing the design methodology for a particular error resilience mechanism or has attempted to understand the benefits from error resilience for a particular processor design. There is no work, to the best of our knowledge, that attempts to understand the benefits of co-optimizing microarchitecture and error resilience. In this paper, we present the first study on co-optimizing a processor pipeline and an error resilience mechanism. We develop an analytical model that relates the benefits from error resiliency to the depth of the pipeline as well as its circuit structure. The model is then used to determine the optimal pipeline depth for different energy efficiency metrics for different error resilience overheads. Our results demonstrate that several interesting relationships exist between error resilience and pipeline structure. For example, we show that there are significant energy efficiency benefits to pipelining an architecture for an error resiliency mechanism vs error resiliency-agnostic pipelining. As another example, we show that benefits from error resiliency are greater for short pipelines than long pipelines. We also confirm that the benefits from error resiliency are higher when the circuit structure is such that error rate increases slowly on reducing input voltage vs a circuit optimized for power where a slack wall exists at the nominal operating point. Finally, we quantify the difference in benefits from error resiliency for irregular vs regular workloads and show that benefits from error resiliency are higher for irregular workloads. Our analytical results were validated using a cycle-accurate simulation-based model.

Original languageEnglish (US)
Title of host publication2010 IEEE International Conference on Computer Design, ICCD 2010
Pages356-363
Number of pages8
DOIs
StatePublished - Dec 1 2010
Event28th IEEE International Conference on Computer Design, ICCD 2010 - Amsterdam, Netherlands
Duration: Oct 3 2010Oct 6 2010

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

Other28th IEEE International Conference on Computer Design, ICCD 2010
CountryNetherlands
CityAmsterdam
Period10/3/1010/6/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Zea, N., Sartori, J., Ahrens, B., & Kumar, R. (2010). Optimal power/Performance pipelining for error resilient processors. In 2010 IEEE International Conference on Computer Design, ICCD 2010 (pp. 356-363). [5647702] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2010.5647702