The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.