Optimal low power XOR gate decomposition

H. Zhou, D. F. Wong

Research output: Contribution to journalConference articlepeer-review


With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low power decomposition of an XOR gate, if the implementation technology is static CMOS logic, previous research gave an O(n log n) time algorithm which assumes that the inputs have both polarities available. But that approach can not be used in dynamic logic. In this paper, we analyze the properties of optimal XOR decompositions in dynamic logic. Based on these optimality properties, we design an optimal algorithm to solve the low power XOR decomposition problem in dynamic logic. We also point out that the previous solution for static logic is not optimal, and given an optimal algorithm which does not even change the input polarities.

Original languageEnglish (US)
Pages (from-to)104-107
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - 2000
Externally publishedYes
EventDAC 2000: 37th Design Automation Conference - Los Angeles, CA, USA
Duration: Jun 5 2000Jun 9 2000

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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