Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors

Danbee Park; Jungseob Lee; Nam Sung Kim; Taewhan Kim

doi:10.1109/ICCAD.2010.5653652

Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors

Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functional units in microprocessor during the code execution, so that the leakage power is maximally saved. Precisely, based on an execution profile of code containing conditional braches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions into code with the objective of minimzing the expected total leakage power while considerig the power and delay overhead on power gating.

Original language	English (US)
Title of host publication	2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	361-364
Number of pages	4
ISBN (Print)	9781424481927
DOIs	https://doi.org/10.1109/ICCAD.2010.5653652
State	Published - 2010
Externally published	Yes
Event	2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States Duration: Nov 7 2010 → Nov 11 2010

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)	1092-3152

Other

Other	2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Country/Territory	United States
City	San Jose, CA
Period	11/7/10 → 11/11/10

ASJC Scopus subject areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Online availability

10.1109/ICCAD.2010.5653652

Library availability

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Cite this

Park, D., Lee, J., Kim, N. S., & Kim, T. (2010). Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. In 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 (pp. 361-364). Article 5653652 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2010.5653652

Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. / Park, Danbee; Lee, Jungseob; Kim, Nam Sung et al.
2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010. Institute of Electrical and Electronics Engineers Inc., 2010. p. 361-364 5653652 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, D, Lee, J, Kim, NS & Kim, T 2010, Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. in 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010., 5653652, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, Institute of Electrical and Electronics Engineers Inc., pp. 361-364, 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, United States, 11/7/10. https://doi.org/10.1109/ICCAD.2010.5653652

Park D, Lee J, Kim NS, Kim T. Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. In 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010. Institute of Electrical and Electronics Engineers Inc. 2010. p. 361-364. 5653652. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). doi: 10.1109/ICCAD.2010.5653652

Park, Danbee ; Lee, Jungseob ; Kim, Nam Sung et al. / Optimal algorithm for profile-based power gating : A compiler technique for reducing leakage on execution units in microprocessors. 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010. Institute of Electrical and Electronics Engineers Inc., 2010. pp. 361-364 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

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Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors

Abstract

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ASJC Scopus subject areas

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