Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors

Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functional units in microprocessor during the code execution, so that the leakage power is maximally saved. Precisely, based on an execution profile of code containing conditional braches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions into code with the objective of minimzing the expected total leakage power while considerig the power and delay overhead on power gating.

Original languageEnglish (US)
Title of host publication2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Pages361-364
Number of pages4
DOIs
StatePublished - Dec 1 2010
Externally publishedYes
Event2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
Duration: Nov 7 2010Nov 11 2010

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
CountryUnited States
CitySan Jose, CA
Period11/7/1011/11/10

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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